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» Synthesis of Testable RTL Designs
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DAC
2007
ACM
15 years 10 months ago
Layered Switching for Networks on Chip
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To s...
Zhonghai Lu, Ming Liu, Axel Jantsch
ISVLSI
2002
IEEE
155views VLSI» more  ISVLSI 2002»
15 years 2 months ago
A High Speed Shift-Invariant Wavelet Transform Chip for Video Compression
Wavelet-based video compression can provide improved codec and bit rates. The shift-variance problem of the discrete wavelet transform on image sequences, however, may cause large...
Henry Y. H. Chuang, David P. Birch, Li-Chang Liu, ...
FCCM
2011
IEEE
241views VLSI» more  FCCM 2011»
14 years 1 months ago
Multilevel Granularity Parallelism Synthesis on FPGAs
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
Alexandros Papakonstantinou, Yun Liang, John A. St...
CODES
2005
IEEE
15 years 3 months ago
The design of a smart imaging core for automotive and consumer applications: a case study
This paper describes the design of a low-cost, low-power smart imaging core that can be embedded in cameras. The core integrates an ARM 9 processor, a camera interface and two spe...
Wido Kruijtzer, Winfried Gehrke, Víctor Rey...
VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
15 years 3 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran