87 search results - page 6 / 18 » Synthesis of Testable RTL Designs |
FPL
2005
Springer
15 years 2 months ago
2005
Springer
Modern heterogeneous FPGAs contain “hard” specificpurpose structures such as blocks of memory and multipliers in addition to the completely flexible “soft” programmable ...
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ICCD
2005
IEEE
15 years 6 months ago
2005
IEEE
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
The algorithms used in wireless applications are increasingly more sophisticated and consequently more challenging to implement in hardware. Traditional design flows require devel...
ASPDAC
2001
ACM
15 years 1 months ago
2001
ACM
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
DAC
1991
ACM
15 years 28 days ago
1991
ACM
-Conventionallyself-test hardware is added after synthesis is completed. For highly sequential circuits like controllersthis design method eitherleads to high hardware overheadsor ...