87 search results - page 9 / 18 » Synthesis of Testable RTL Designs |
129
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DAC
1999
ACM
16 years 4 months ago
1999
ACM
This paper presents a synthesis tool ICEBERG for embedded in-circuit emulators (ICE's), that are part of the development environment for microcontroller (or microprocessor)-b...
148
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ISLPED
2009
ACM
15 years 10 months ago
2009
ACM
Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care (ODC) conditions. In this paper we presen...
129
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DAC
2003
ACM
16 years 4 months ago
2003
ACM
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...
138
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VTS
2007
IEEE
15 years 10 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
146
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ICCAD
2004
IEEE
16 years 24 days ago
2004
IEEE
— Cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent in...