3 search results - page 1 / 1 » Synthesis of a novel timing-error detection architecture |
98
Voted
TODAES
2008
15 years 7 days ago
2008
VLSID
2002
IEEE
16 years 2 months ago
2002
IEEE
We propose the redundancy identification of wire replacement faults. The solutions rely on the satisfiability (SAT) formulation of redundancy identification, augmented with the me...
114
Voted
DAC
2003
ACM
16 years 2 months ago
2003
ACM
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...