30 search results - page 3 / 6 » Synthesis of system verilog assertions |
EH
2003
IEEE
13 years 11 months ago
2003
IEEE
This paper describes a multi-objective Evolutionary Algorithm (EA) system for the synthesis of efficient non-linear VLSI circuit modules. The EA takes the specification for a no...
FMCAD
2008
Springer
13 years 7 months ago
2008
Springer
The semantics of temporal logic is usually defined with respect to a word representing a computation path over a set of atomic propositions. A temporal logic formula does not contr...
MSE
2005
IEEE
13 years 12 months ago
2005
IEEE
A graduate-level computer engineering course sequence at the OGI School of Science and Engineering teaches state-of-the-art digital system design practices and system-on-chip desi...
ICALP
2009
Springer
14 years 6 months ago
2009
Springer
The IEEE standardized Property Specification Language, PSL for short, extends the well-known linear-time temporal logic LTL with so-called semi-extended regular expressions. PSL an...
FMCAD
2009
Springer
14 years 25 days ago
2009
Springer
Abstract—Symbolic Trajectory Evaluation is an industrialstrength verification method, based on symbolic simulation and abstraction, that has been highly successful in data path ...