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ICCD
1997
IEEE
87views Hardware» more  ICCD 1997»
15 years 8 months ago
Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits
Speed, cost and correctness may be the most important factors in designing a digital system. This paper proposes a novel and general methodology to synthesize iterative functions ...
Fu-Chiung Cheng
ICMCS
2005
IEEE
172views Multimedia» more  ICMCS 2005»
15 years 10 months ago
A Study of Synthesizing New Human Motions from Sampled Motions Using Tensor Decomposition
This paper applies an algorithm, based on Tensor Decomposition, to a new synthesis application: by using sampled motions of people of different ages under different emotional stat...
Rovshan Kalanov, Jieun Cho, Jun Ohya
GLVLSI
2003
IEEE
166views VLSI» more  GLVLSI 2003»
15 years 9 months ago
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe
DFT
2009
IEEE
155views VLSI» more  DFT 2009»
15 years 11 months ago
Errors in DNA Self-Assembly by Synthesized Tile Sets
This paper presents a study of errors that occur in DNA self-assembly using synthesized tile sets for template manufacturing. It is shown that due to the reduced size, aggregates ...
Xiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabri...
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
15 years 10 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen