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133
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DATE
2008
IEEE
15 years 11 months ago
2008
IEEE
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...
122
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ISCAS
2008
IEEE
15 years 11 months ago
2008
IEEE
—A simple low-area and low-power clock frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. In this circuit, 2n voltage controlled delay lines (...
111
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ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
—This paper presents a 2GHz 8-bit CMOS ROM-less direct digital frequency synthesizer (DDFS). Nonlinear current steering digital to analog converter (DAC) has been utilized to con...
129
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EDCC
2005
Springer
15 years 10 months ago
2005
Springer
Abstract. Current paper proposes an efficient alternative for traditional gatelevel fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSB...
133
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MM
2003
ACM
15 years 9 months ago
2003
ACM
This paper presents a novel method to recover lost packets in music streaming using a synthesizer to generate percussive sounds. As an improvement of the state-of-the-art system t...