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DATE
2010
IEEE
107views Hardware» more  DATE 2010»
15 years 10 months ago
An error-correcting unordered code and hardware support for robust asynchronous global communication
A new delay-insensitive data encoding scheme for global asynchronous communication is introduced. The goal of this work is to combine the timing-robustness of delay-insensitive (i....
Melinda Y. Agyekum, Steven M. Nowick
157
Voted
DATE
2010
IEEE
113views Hardware» more  DATE 2010»
15 years 10 months ago
PM-COSYN: PE and memory co-synthesis for MPSoCs
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
PLDI
2010
ACM
15 years 10 months ago
Smooth interpretation
We present smooth interpretation, a method to systematically approximate numerical imperative programs by smooth mathematical functions. This approximation facilitates the use of ...
Swarat Chaudhuri, Armando Solar-Lezama
164
Voted
ICTAI
2002
IEEE
15 years 10 months ago
On Temporal Planning as CSP
(Appears as a regular paper in the proceedings of IEEE International Conference on Tools with Artificial Intelligence (ICTAI), IEEE Computer Society, Washington D.C. Nov. 2002, p...
Amol Dattatraya Mali
MICRO
2002
IEEE
171views Hardware» more  MICRO 2002»
15 years 10 months ago
Orion: a power-performance simulator for interconnection networks
With the prevalence of server blades and systems-ona-chip (SoCs), interconnection networks are becoming an important part of the microprocessor landscape. However, there is limite...
Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad...