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FPGA
2008
ACM
168views FPGA» more  FPGA 2008»
15 years 6 months ago
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs
The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an ...
Alessandro Cevrero, Panagiotis Athanasopoulos, Had...
141
Voted
DAC
2010
ACM
15 years 5 months ago
Automatic multithreaded pipeline synthesis from transactional datapath specifications
We present a technique to automatically synthesize a multithreaded in-order pipeline from a high-level unpipelined datapath specification. This work extends the previously propose...
Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timo...
CATA
2010
15 years 5 months ago
A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog
In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consum...
Bahram Hakhamaneshi, Behnam S. Arad
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
15 years 5 months ago
Automatic pipelining from transactional datapath specifications
Abstract—We present a transactional datapath specification (Tspec) and the tool (T-piper) to synthesize automatically an inpelined implementation from it. T-spec abstractly views...
Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-...
145
Voted
ENTCS
2010
99views more  ENTCS 2010»
15 years 5 months ago
Describing Secure Interfaces with Interface Automata
Interface automata are a model that allows for the representation of stateful interfaces. In this paper we introduce a variant of interface automata, which we call interface struc...
Matias Lee, Pedro R. D'Argenio