Sciweavers

11 search results - page 2 / 3
» Synthesizing Iterative Functions into Delay-Insensitive Tree...
Sort
View
ICCAD
1997
IEEE
97views Hardware» more  ICCAD 1997»
13 years 10 months ago
Low power logic synthesis for XOR based circuits
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...
Unni Narayanan, C. L. Liu
DAC
1997
ACM
13 years 10 months ago
A Graph-Based Synthesis Algorithm for AND/XOR Networks
In this paper, we introduce a Shared Multiple Rooted XORbased Decomposition Diagram XORDD to represent functions with multiple outputs. Based on the XORDD representation, we dev...
Yibin Ye, Kaushik Roy
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
13 years 11 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
13 years 9 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
DAC
1998
ACM
13 years 10 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha