3 search results - page 1 / 1 » Synthesizing checkers for on-line verification of System-on-... |
ISCAS
2003
IEEE
15 years 4 months ago
2003
IEEE
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...
79
Voted
FDL
2008
IEEE
15 years 19 days ago
2008
IEEE
In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from...
95
Voted
GPCE
2007
Springer
15 years 5 months ago
2007
Springer
Programs of a software product line can be synthesized by composing modules that implement features. Besides high-level domain constraints that govern the compatibility of feature...