Sciweavers

198 search results - page 15 / 40
» Synthesizing racy tests
Sort
View
ATS
2005
IEEE
139views Hardware» more  ATS 2005»
15 years 3 months ago
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability
— Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance, can result in improved test cost and test confid...
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
DATE
1998
IEEE
110views Hardware» more  DATE 1998»
15 years 1 months ago
Scheduling and Module Assignment for Reducing Bist Resources
Built-in self-test BIST techniques modify functional hardware to give a data path the capability to test itself. The modi cation of data path registers into registers BIST resourc...
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breue...
VTS
1996
IEEE
111views Hardware» more  VTS 1996»
15 years 1 months ago
Synthesis-for-scan and scan chain ordering
Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By t...
Robert B. Norwood, Edward J. McCluskey
DSD
2005
IEEE
96views Hardware» more  DSD 2005»
14 years 11 months ago
Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
Peter Filter, Hana Kubatova
112
Voted
IJDAR
2002
116views more  IJDAR 2002»
14 years 9 months ago
Performance evaluation of pattern classifiers for handwritten character recognition
Abstract. This paper describes a performance evaluation study in which some efficient classifiers are tested in handwritten digit recognition. The evaluated classifiers include a s...
Cheng-Lin Liu, Hiroshi Sako, Hiromichi Fujisawa