198 search results - page 19 / 40 » Synthesizing racy tests |
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
DEXA
2000
Springer
15 years 2 months ago
2000
Springer
This paper describes a new benchmark for object-relational DBMSs, the Benchmark for Object-Relational Databases (BORD). BORD has been developed to evaluate system performance pecul...
DATE
1998
IEEE
15 years 1 months ago
1998
IEEE
We extend the subsequence removal technique to provide signi cantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to ident...
ITC
1996
IEEE
15 years 1 months ago
1996
IEEE
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
112
Voted
ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some seri...