10159 search results - page 10 / 2032 » System Design Validation Using Formal Models |
DAC
2007
ACM
15 years 1 months ago
2007
ACM
We present a framework for validating the compliance of a design with a given architecture. Our approach is centered on the concept of misinterpretations. These include missing be...
94
Voted
ICRE
1998
IEEE
15 years 1 months ago
1998
IEEE
Model checking is shown to be an effective tool in validating the behavior of a fault tolerant embedded spacecraft controller. The case study presented here at by judiciously abst...
DAC
1998
ACM
15 years 10 months ago
1998
ACM
Successive, formal refinement is a new approach for specification of embedded systems using a general-purpose programming language. Systems are formally modeled as Abstractable Sy...
BIRTHDAY
2010
Springer
14 years 10 months ago
2010
Springer
Abstract. To support model-based development and analysis of embedded systems, the specification language VDM++ has been extended with asynchronous communication and improved timin...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...