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» System Design Validation Using Formal Models
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ZUM
2000
Springer
15 years 6 months ago
Formal Methods for Industrial Products
We have recently completed the specication and security proof of a large, industrial scale application. The application is security critical, and the modelling and proof were done ...
Susan Stepney, David Cooper
WOTE
2010
15 years 9 days ago
Verifying Privacy-Type Properties of Electronic Voting Protocols: A Taster
Abstract. While electronic elections promise the possibility of convenient, efficient and secure facilities for recording and tallying votes, recent studies have highlighted inadeq...
Stéphanie Delaune, Steve Kremer, Mark Ryan
150
Voted
SIGSOFT
2003
ACM
16 years 3 months ago
Towards scalable compositional analysis by refactoring design models
Automated finite-state verification techniques have matured considerably in the past several years, but state-space explosion remains an obstacle to their use. Theoretical lower b...
Yung-Pin Cheng, Michal Young, Che-Ling Huang, Chia...
UML
2001
Springer
15 years 7 months ago
A Formal Mapping between UML Static Models and Algebraic Specifications
: There are several reasons to specify UML models in a formal way The most important are to avoid inconsistencies and ambiguities and to do verification and forecasting of system p...
Liliana Favre
123
Voted
CERA
2002
134views more  CERA 2002»
15 years 2 months ago
Design Parameterization for Concurrent Design and Manufacturing of Mechanical Systems
Design changes are frequently encountered in the product development process. The complexity of the design changes is multiplied when the product design involves multiple engineer...
Javier Silva, Kuang-Hua Chang