10159 search results - page 278 / 2032 » System Design Validation Using Formal Models |
106
Voted
IEEEPACT
2007
IEEE
15 years 9 months ago
2007
IEEE
The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable. Howe...
108
Voted
CONTEXT
2007
Springer
15 years 9 months ago
2007
Springer
The paper focuses on a difficult problem when formalizing knowledge: What about the possible concepts that didn’t make it into the formalization? We call such concepts the uncons...
114
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IWIA
2005
IEEE
15 years 9 months ago
2005
IEEE
This paper proposes a methodology to develop countermeasures against code injection attacks, and validates the methodology by working out a specific countermeasure. This methodol...
125
Voted
ECTEL
2007
Springer
15 years 9 months ago
2007
Springer
: Current learning modelling languages do not allow formalization of scripts where generic tools are required. This limitation is especially relevant on remote courses when using c...
123
Voted
IFM
2000
Springer
15 years 7 months ago
2000
Springer
This paper presents a formal language for the design of component-based enterprise system. The language (StAC) allows the usual parallel and sequential behaviours, but most signifi...