10159 search results - page 319 / 2032 » System Design Validation Using Formal Models |
156
Voted
EHCI
1998
15 years 5 months ago
1998
: Task models bridge the gap between HCI and Software Engineering. They are useful both for interface design and for generating user interface code and user documentation. These be...
127
Voted
CHI
2005
ACM
16 years 4 months ago
2005
ACM
This paper presents the design, implementation and validation of an enhanced mobile phone messaging system (DeDe), allowing the sender to define the context in which the message w...
126
Voted
ISVLSI
2007
IEEE
15 years 10 months ago
2007
IEEE
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
155
Voted
JUCS
2002
15 years 3 months ago
2002
: This paper presents a framework for representing formal semantics of a subset of the Unified Modeling Language (UML) notation in a higher-order logic, more specifically semantics...
130
Voted
KBSE
1999
IEEE
15 years 8 months ago
1999
IEEE
This paper describes the application of advanced formal modelling techniques and tools from the CADP toolset to the verification of CFS, a distributed file system kernel. After a ...