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DSD
2009
IEEE
88views Hardware» more  DSD 2009»
15 years 2 months ago
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor
Abstract--The implementation of an efficient result forwarding unit for asynchronous processors faces the problem of the inherent lack of synchronisation between result producer an...
Luis A. Tarazona, Doug A. Edwards, Luis A. Plana
144
Voted
SC
2009
ACM
15 years 9 months ago
A framework for core-level modeling and design of reconfigurable computing algorithms
Reconfigurable computing (RC) is rapidly becoming a vital technology for many applications, from high-performance computing to embedded systems. The inherent advantages of custom-...
Gongyu Wang, Greg Stitt, Herman Lam, Alan D. Georg...
VIS
2008
IEEE
172views Visualization» more  VIS 2008»
16 years 6 months ago
Color Design for Illustrative Visualization
Professional designers and artists are quite cognizant of the rules that guide the design of effective color palettes, from both aesthetic and attention-guiding points of view. In ...
Lujin Wang, Joachim Giesen, Kevin T. McDonnell, ...
ICCAD
1995
IEEE
144views Hardware» more  ICCAD 1995»
15 years 8 months ago
Background memory management for dynamic data structure intensive processing systems
Abstract -- Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently availab...
Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wu...
ERSA
2004
86views Hardware» more  ERSA 2004»
15 years 6 months ago
Incremental Timing Budget Management in Programmable Systems
Delay budget is an excess delay that each component of a design can tolerate under a given timing constraint. Delay budgeting has been widely exploited to improve the design quali...
Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahas...