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ASPLOS
2011
ACM
14 years 8 months ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
153
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MOBISYS
2011
ACM
14 years 7 months ago
Opportunistic alignment of advertisement delivery with cellular basestation overloads
This paper is motivated by two observations: (1) cellular network operators are actively exploring advertisement delivery as a new means of revenue generation, and (2) cellular ba...
Ravi Kokku, Rajesh Mahindra, Sampath Rangarajan, H...
RTCSA
2007
IEEE
15 years 11 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
FPL
2005
Springer
98views Hardware» more  FPL 2005»
15 years 10 months ago
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow
This paper describes a method based on polynomial approximation for transferring ROM resources used in FPGA designs to multiplication and addition operations. The technique can be...
Gareth W. Morris, George A. Constantinides, Peter ...
SIGGRAPH
2000
ACM
15 years 9 months ago
Escherization
This paper introduces and presents a solution to the “Escherization” problem: given a closed figure in the plane, find a new closed figure that is similar to the original a...
Craig S. Kaplan, David Salesin