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DATE
2004
IEEE
158views Hardware» more  DATE 2004»
15 years 10 months ago
Communication Analysis for System-On-Chip Design
In this paper we present an approach for analysis of systems of parallel, communicating processes for SoC design. We present a method to detect communications that synchronize the...
Axel Siebenborn, Oliver Bringmann, Wolfgang Rosens...
ISCA
2011
IEEE
269views Hardware» more  ISCA 2011»
14 years 10 months ago
Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
High assurance systems used in avionics, medical implants, and cryptographic devices often rely on a small trusted base of hardware and software to manage the rest of the system. ...
Mohit Tiwari, Jason Oberg, Xun Li 0001, Jonathan V...
INFOCOM
2000
IEEE
15 years 10 months ago
Design, Implementation and Performance of a Content-Based Switch
Abstract— In this paper, we share our experience in designing and building a content based switch which we call L5. In addition to the layer 2-3-4 information available in the pa...
George Apostolopoulos, David Aubespin, Vinod G. J....
FPL
2009
Springer
132views Hardware» more  FPL 2009»
15 years 10 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
DATE
2010
IEEE
160views Hardware» more  DATE 2010»
15 years 11 months ago
Soft error-aware design optimization of low power and time-constrained embedded systems
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
Rishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu...