4887 search results - page 192 / 978 » System Level Design Using C |
141
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CODES
2006
IEEE
15 years 11 months ago
2006
IEEE
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
145
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SBACPAD
2007
IEEE
15 years 11 months ago
2007
IEEE
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
132
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DAC
2006
ACM
16 years 6 months ago
2006
ACM
Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...
119
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CIMCA
2006
IEEE
15 years 11 months ago
2006
IEEE
On-line trading or Internet Commerce restoring to ECommerce systems are gradually replacing the traditional commerce activities. Internet users must have reasonable faith on the u...
193
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DILS
2009
Springer
15 years 9 months ago
2009
Springer
Abstract. Data integration plays a major role in modern Life Sciences research primarily because required resources are geographically distributed across continents and experts dep...