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TC
1998
15 years 1 months ago
Design Verification of the S3.mp Cache-Coherent Shared-Memory System
—This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable emory MultiProcessor (S3.mp) at three levels of abstracti...
Fong Pong, Michael C. Browne, Gunes Aybay, Andreas...
DATE
2008
IEEE
168views Hardware» more  DATE 2008»
15 years 8 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
EUROMICRO
1999
IEEE
15 years 6 months ago
Software Synthesis for System Level Design Using Process Execution Trees
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
Leo J. van Bokhoven, Jeroen Voeten, Marc Geilen
96
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IEEECIT
2005
IEEE
15 years 7 months ago
iCDMdt: Focused the Model Mapping and Performance Optimization in Embedded System Design
This paper proposes a method of model-driven HW/SW co-design in embedded system design and discusses the key technology of model mapping, automatic generating codes and performanc...
Jing Luan, Xuan Cheng, Junzhong Gu
SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
15 years 8 months ago
REDEFIS: a system with a redefinable instruction set processor
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
Victor M. Goulart Ferreira, Lovic Gauthier, Takayu...