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DATE
2006
IEEE
119views Hardware» more  DATE 2006»
15 years 8 months ago
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
118
Voted
DAC
2007
ACM
16 years 3 months ago
Parameterized Macromodeling for Analog System-Level Design Exploration
In this paper we propose a novel parameterized macromodeling technique for analog circuits. Unlike traditional macromodels that are only extracted for a small variation space, our...
Jian Wang, Xin Li, Lawrence T. Pileggi
DATE
2005
IEEE
118views Hardware» more  DATE 2005»
15 years 7 months ago
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach
In this paper, we present a methodology for customized communication architecture synthesis that matches the communication requirements of the target application. This is an impor...
Ümit Y. Ogras, Radu Marculescu
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
15 years 8 months ago
A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design
The industry is merging two different Wireless Personal Area Networks (WPAN) technologies: Bluetooth (BT) and WiMedia Ultra Wide Band (UWB), into a single BT over UWB (BToUWB) spe...
Alexandre Lewicki, Javier del Prado Pavon, Jacky T...
DAC
2005
ACM
16 years 3 months ago
Simulation based deadlock analysis for system level designs
In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the ...
Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. S...