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IC3
2009
15 years 4 months ago
Multi-scale Modeling and Analysis of Nano-RFID Systems on HPC Setup
In this paper we have worked out on some the complex modeling aspects such as Multi Scale modeling, MATLAB Sugar based modeling and have shown the complexities involved in the anal...
Rohit Pathak, Satyadhar Joshi
TII
2010
146views Education» more  TII 2010»
15 years 1 months ago
PAUC: Power-Aware Utilization Control in Distributed Real-Time Systems
Abstract--CPU utilization control has recently been demonstrated to be an effective way of meeting end-to-end deadlines for distributed real-time systems running in unpredictable e...
Xiaorui Wang, Xing Fu, Xue Liu, Zonghua Gu
SIGMETRICS
1992
ACM
128views Hardware» more  SIGMETRICS 1992»
15 years 10 months ago
MemSpy: Analyzing Memory System Bottlenecks in Programs
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...
Margaret Martonosi, Anoop Gupta, Thomas E. Anderso...
ARCS
2009
Springer
16 years 28 days ago
Empirical Performance Models for Java Workloads
Abstract. Java is widely deployed on a variety of processor architectures. Consequently, an understanding of microarchitecture level Java performance is critical to optimize curren...
Pradeep Rao, Kazuaki Murakami
TVLSI
2008
164views more  TVLSI 2008»
15 years 6 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...