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FPL
2004
Springer
83views Hardware» more  FPL 2004»
15 years 7 months ago
System-Level Modeling of Dynamically Reconfigurable Co-processors
Dynamically reconfigurable co-processors (DRCs) are interesting design alternatives when both flexibility and performance are concerns. However, it is difficult to study the perfor...
Yang Qu, Kari Tiensyrjä, Kostas Masselos
106
Voted
AHS
2007
IEEE
247views Hardware» more  AHS 2007»
15 years 8 months ago
Hybrid Communication Medium for Adaptive SoC Architectures
This paper proposes a hybrid communication medium for on-chip communication targeting adaptive SoC architectures. Unlike the work carried out in literature, where the term “hybr...
Balal Ahmad, Ali Ahmadinia, Tughrul Arslan
111
Voted
DATE
2009
IEEE
130views Hardware» more  DATE 2009»
15 years 9 months ago
Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA
—IP-XACT is a standard for describing intellectual property metadata for System-on-Chip (SoC) integration. Reesearchers have proposed visualizing and abstracting IP-XACT objects ...
Tero Arpinen, Tapio Koskinen, Erno Salminen, Timo ...
NDSS
2007
IEEE
15 years 8 months ago
Generic Application-Level Protocol Analyzer and its Language
Application-level protocol analyzers are important components in tools such as intrusion detection systems, firewalls, and network monitors. Currently, protocol analyzers are wri...
Nikita Borisov, David Brumley, Helen J. Wang, John...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
15 years 8 months ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...