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CODES
2007
IEEE
15 years 8 months ago
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels
In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a re...
Chen-Ling Chou, Radu Marculescu
WRAC
2005
Springer
15 years 11 months ago
Characterizing Environmental Information for Monitoring Agents
A multiagent architecture for vehicle and structural health monitoring is proposed. A prototype using this architecture was developed using JADE. Critical aspects of the design wer...
Albert C. Esterline, Bhanu Gandluri, Mannur Sundar...
TVLSI
2010
15 years 25 days ago
Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding
By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density ad...
Shu Li, Tong Zhang
DAC
2004
ACM
16 years 7 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
EVOW
2010
Springer
16 years 1 months ago
Towards a Generic Framework for Automated Video Game Level Creation
This paper presents a generative system for the automatic creation of video game levels. Our approach is novel in that it allows high-level design goals to be expressed in a top-do...
Nathan Sorenson, Philippe Pasquier