12333 search results - page 156 / 2467 » System Level Modelling for Hardware Software Systems |
146
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
In this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurat...
151
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DATE
2007
IEEE
16 years 17 days ago
2007
IEEE
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
177
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ISCA
1994
IEEE
15 years 10 months ago
1994
IEEE
We comparethe performance of software-supported shared memory on a general-purpose network to hardware-supported shared memory on a dedicated interconnect. Up to eight processors,...
152
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
158
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HICSS
2005
IEEE
15 years 12 months ago
2005
IEEE
In the past decade outsourcing a software system’s support and maintenance has become relatively common across most organizations. In this paper we consider a few issues governi...