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154
Voted
DATE
1998
IEEE
141views Hardware» more  DATE 1998»
15 years 10 months ago
Address Bus Encoding Techniques for System-Level Power Optimization
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I...
Luca Benini, Giovanni De Micheli, Donatella Sciuto...
ISSS
1997
IEEE
103views Hardware» more  ISSS 1997»
15 years 10 months ago
Fast and Extensive System-Level Memory Exploration for ATM Applications
In this paper, our memory architecture exploration methodology and CAD techniques for network protocol applications are presented. Prototype tools have been implemented, and appli...
Peter Slock, Sven Wuytack, Francky Catthoor, Gjalt...
ANCS
2010
ACM
15 years 4 months ago
The case for hardware transactional memory in software packet processing
Software packet processing is becoming more important to enable differentiated and rapidly-evolving network services. With increasing numbers of programmable processor and acceler...
Martin Labrecque, J. Gregory Steffan
FDL
2004
IEEE
15 years 10 months ago
UML System-Level Analysis and Design of Secure Communication Schemes for Embedded Systems
In this work we develop a secure communication protocol in the context of a Remote Meter Reading (RMR) System. We first analyze existing standards in secure communication (e.g. IP...
Mauro Prevostini, Giuseppe Piscopo, I. Stefanini
157
Voted
ISSS
1997
IEEE
103views Hardware» more  ISSS 1997»
15 years 10 months ago
A Source-Level Dynamic Analysis Methodology and Tool for High-Level Synthesis
This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level de...
Chih-Tung Chen, Kayhan Küçük&cced...