12333 search results - page 178 / 2467 » System Level Modelling for Hardware Software Systems |
146
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ITC
2003
IEEE
15 years 11 months ago
2003
IEEE
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
169
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DATE
2000
IEEE
15 years 10 months ago
2000
IEEE
Recently a number of heuristic based system-level synthesis algorithms have been proposed. Though these algorithms quickly generate good solutions, how close these solutions are t...
187
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ICCD
2000
IEEE
15 years 10 months ago
2000
IEEE
A major obstacle to widespread acceptance of formal verification is the difficulty in using the tools effectively. Although learning the basic syntax and operation of a formal ver...
176
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ISQED
2007
IEEE
16 years 19 days ago
2007
IEEE
With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-sca...
172
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HASE
1999
IEEE
15 years 10 months ago
1999
IEEE
The paper introduces a method to model embedded dependability-critical systems as AND-composition of Guarded Statecharts which are special UMLstatecharts. With Guarded Statecharts...