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» System Level Modelling for Hardware Software Systems
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DAC
1997
ACM
15 years 8 months ago
A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...
Claus Schneider
RTSS
2008
IEEE
15 years 11 months ago
Hardware Runtime Monitoring for Dependable COTS-Based Real-Time Embedded Systems
COTS peripherals are heavily used in the embedded market, but their unpredictability is a threat for high-criticality real-time systems: it is hard or impossible to formally verif...
Rodolfo Pellizzoni, Patrick O'Neil Meredith, Marco...
CORR
2008
Springer
104views Education» more  CORR 2008»
15 years 4 months ago
Policies of System Level Pipeline Modeling
Pipelining is a well understood and often used implementation technique for increasing the performance of a hardware system. We develop several SystemC/C++ modeling techniques tha...
Edwin A. Harcourt
CODES
2009
IEEE
15 years 8 months ago
Cycle count accurate memory modeling in system level design
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
Yi-Len Lo, Mao Lin Li, Ren-Song Tsay
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
15 years 10 months ago
Functional Validation of System Level Static Scheduling
Increase in system level modeling has given rise to a need for efficient functional validation of models above cycle accurate level. This paper presents a technique for comparing...
Samar Abdi, Daniel D. Gajski