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ICPP
2003
IEEE
15 years 3 months ago
Scheduling Algorithms with Bus Bandwidth Considerations for SMPs
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
Christos D. Antonopoulos, Dimitrios S. Nikolopoulo...
EUROPAR
2001
Springer
15 years 2 months ago
VIA Communication Performance on a Gigabit Ethernet Cluster
As the technology for high-speed networks has evolved over the last decade, the interconnection of commodity computers (e.g., PCs and workstations) at gigabit rates has become a re...
Mark Baker, Paul A. Farrell, Hong Ong, Stephen L. ...
ISORC
2008
IEEE
15 years 4 months ago
A Real-Time Java Component Model
The Real-Time Specification for Java (RTSJ) [10] is becoming a popular choice in the world of real-time programming. However, the complexities introduced by RTSJ bring the needs ...
Ales Plsek, Philippe Merle, Lionel Seinturier
FPL
2006
Springer
161views Hardware» more  FPL 2006»
15 years 1 months ago
Predictive Load Balancing for Interconnected FPGAs
A Field Programmable Gate Array (FPGA), when used as a platform for implementing special-purpose computing architectures, offers the potential for increased functional parallelism...
Jason D. Bakos, Charles L. Cathey, Allen Michalski
PRICAI
2000
Springer
15 years 1 months ago
Virtual Enterprise Design - BDI Agents vs. Objects
Current research identifying architectures for a virtual enterprise has moved from information modelling to role modelling. Thus, a high level of autonomy results from the distribu...
Iyad Rahwan, Ryszard Kowalczyk, Yun Yang