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ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 1 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
ASAP
2009
IEEE
98views Hardware» more  ASAP 2009»
14 years 7 months ago
A Power-Scalable Switch-Based Multi-processor FFT
This paper examines the architecture, algorithm and implementation of a switch-based multi-processor realization of the fast Fourier transform (FFT). The architecture employs M pr...
Bassam Jamil Mohd, Earl E. Swartzlander Jr.
MATA
2004
Springer
199views Communications» more  MATA 2004»
15 years 2 months ago
Configuration Management for Networked Reconfigurable Embedded Devices
Distribution of product updates to embedded devices can increase product lifetimes for consumers and boost revenues for vendors. Dynamic provisioning of application solutions to e...
Timothy O'Sullivan, Richard Studdert
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches
In recent years, several alternative devices have been proposed to deal with inherent limitation of conventional CMOS devices in terms of scalability at nanometer scale geometry. ...
Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab
FCCM
2008
IEEE
160views VLSI» more  FCCM 2008»
15 years 4 months ago
Facilitating Processor-Based DPR Systems for non-DPR Experts
Currently, only Xilinx Field Programmable Gate Arrays (FPGAs) support Dynamic Partial Reconfiguration (DPR). While there is currently some Computer Aided Design (CAD) tool support...
Edward Chen, William A. Gruver, Dorian Sabaz, Lesl...