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VLSISP
2008
123views more  VLSISP 2008»
14 years 9 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
PROCEDIA
2010
138views more  PROCEDIA 2010»
14 years 4 months ago
Using the reconfigurable massively parallel architecture COPACOBANA 5000 for applications in bioinformatics
Currently several computational problems require high processing power to handle huge amounts of data, although underlying core algorithms appear to be rather simple. Especially i...
Lars Wienbrandt, Stefan Baumgart, Jost Bissel, Car...
ICRA
2009
IEEE
127views Robotics» more  ICRA 2009»
14 years 7 months ago
Roombots-mechanical design of self-reconfiguring modular robots for adaptive furniture
We aim at merging technologies from information technology, roomware, and robotics in order to design adaptive and intelligent furniture. This paper presents design principles for ...
Alexander Spröwitz, Aude Billard, Pierre Dill...
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
15 years 4 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
FPGA
2006
ACM
195views FPGA» more  FPGA 2006»
15 years 1 months ago
An adaptive Reed-Solomon errors-and-erasures decoder
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
Lilian Atieno, Jonathan Allen, Dennis Goeckel, Rus...