60 search results - page 12 / 12 » System level clock tree synthesis for power optimization |
SENSYS
2010
ACM
13 years 4 months ago
2010
ACM
This paper considers the problem of estimating the power breakdowns for the main appliances inside a building using a small number of power meters and the knowledge of the ON/OFF ...
DAC
2006
ACM
14 years 7 months ago
2006
ACM
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
SLIP
2003
ACM
13 years 11 months ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
PLDI
2003
ACM
13 years 11 months ago
2003
ACM
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
INFOCOM
2008
IEEE
14 years 22 days ago
2008
IEEE
—Wireless communications are inherently symmetric; that is, it takes an attacker the same amount of power to modulate a signal as it does for a legitimate node to modulate the sa...