60 search results - page 3 / 12 » System level clock tree synthesis for power optimization |
93
Voted
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
86
Voted
ICCD
1997
IEEE
15 years 1 months ago
1997
IEEE
DAC
1997
ACM
15 years 1 months ago
1997
ACM
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
ISCAS
2008
IEEE
15 years 3 months ago
2008
IEEE
— In this paper, we have proposed a thermal aware routing based parameterization to generate a clock model that takes the stochastic temperature variation into consideration. The...