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» System level design, a VHDL based approach
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DATE
2003
IEEE
82views Hardware» more  DATE 2003»
15 years 2 months ago
A Solution for Hardware Emulation of Non Volatile Memory Macrocells
More and more the system verification makes use of hardware emulation techniques that allow a speed up in simulation performance up to thousand times. Typically, a design is comp...
Alessandro Pirola
82
Voted
EURODAC
1994
IEEE
120views VHDL» more  EURODAC 1994»
15 years 1 months ago
Generating compilers for generated datapaths
Modern CAD systems allow the designers to come up with powerful programmable datapaths in avery short time. The time to develop compilers for this datapaths is much longer. This p...
Michael Held, Manfred Glesner
92
Voted
CSE
2009
IEEE
15 years 4 months ago
On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals
—In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data pl...
Sebastian Hessel, David Szczesny, Shadi Traboulsi,...
90
Voted
DAC
1997
ACM
15 years 1 months ago
A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...
Claus Schneider
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 3 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...