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78
Voted
DATE
2000
IEEE
15 years 1 months ago
2000
IEEE
This paper presents a methodology for parallel and distributed simulation of VHDL using the PDES (parallel discrete-event simulation) paradigm. To achieve better features and perf...
DATE
1998
IEEE
15 years 1 months ago
1998
IEEE
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the ...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
70
Voted
EURODAC
1994
IEEE
1994
IEEE
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
15 years 1 months ago
: This paper presents an approach to high-level synthesis which is based upon a 0/1 integer programming model. In contrast to other approaches, this model allows solving all three ...