5744 search results - page 5 / 1149 » System level design, a VHDL based approach |
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EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
The paper presents an approach for performance and complexity analysis of hardware/software implementations for real-time systems on every stage of the partitioning. There are two...
EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
This paper describes the features and design methodology of MIDA, a MPEG1 integrated audio decoder. MIDA has been almost completely designed using automatic synthesis of VHDL desc...
ASPDAC
2001
ACM
15 years 1 months ago
2001
ACM
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
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ISSS
2000
IEEE
15 years 1 months ago
2000
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
RTAS
2009
IEEE
15 years 4 months ago
2009
IEEE
Embedded systems in safety-critical environments demand safety guarantees while providing many useful services that are too complex to formally verify or fully test. Existing appl...