897 search results - page 103 / 180 » System-Level Design for FPGAs |
118
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DAC
2002
ACM
16 years 5 months ago
2002
ACM
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput ...
120
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DATE
2009
IEEE
15 years 11 months ago
2009
IEEE
This paper presents a design methodology for fully reconfigurable low-voltage Delta-Sigma converters as for instance used in next-generation wireless applications. The design metho...
123
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ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
188
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ARCS
2012
Springer
14 years 7 days ago
2012
Springer
: This paper presents a novel approach to efficiently perform early system level design space exploration (DSE) of MultiProcessor System-on-Chip (MPSoC) based embedded systems. By...
128
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DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
Most of the challenges related to the development of multi-processor platforms for complex wireless and multimedia applications fall into the Electronic System Level (ESL) domain....