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» System-Level Design for FPGAs
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CSE
2009
IEEE
15 years 11 months ago
On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals
—In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data pl...
Sebastian Hessel, David Szczesny, Shadi Traboulsi,...
182
Voted
TCOS
2010
14 years 11 months ago
Green Secure Processors: Towards Power-Efficient Secure Processor Design
With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the softwar...
Siddhartha Chhabra, Yan Solihin
CODES
1999
IEEE
15 years 8 months ago
How standards will enable hardware/software co-design
o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...
Mark Genoe, Christopher K. Lennard, Joachim Kunkel...
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
16 years 4 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood
142
Voted
RSP
1999
IEEE
122views Control Systems» more  RSP 1999»
15 years 8 months ago
Incremental Compilation for Logic Emulation
Over the past decade, the steady growth rate of FPGA device capacities has enabled the development of multi-FPGA prototyping environments capable of implementing millions of logic...
Russell Tessier