897 search results - page 113 / 180 » System-Level Design for FPGAs |
139
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SAMOS
2007
Springer
15 years 10 months ago
2007
Springer
—This paper presents a new methodology based on evolutionary multi-objective optimization (EMO) to synthesize multiple complex modules on programmable devices (FPGAs). It starts ...
213
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ANCS
2011
ACM
14 years 4 months ago
2011
ACM
Network virtualization has emerged as a powerful technique to deploy novel services and experimental protocols over shared network infrastructures. Although recent research has hi...
156
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FPGA
2003
ACM
15 years 9 months ago
2003
ACM
One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywher...
128
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ICCAD
2004
IEEE
16 years 1 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
133
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ICCAD
1994
IEEE
15 years 8 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...