897 search results - page 114 / 180 » System-Level Design for FPGAs |
152
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FPGA
2010
ACM
16 years 1 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
160
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DAC
2004
ACM
16 years 5 months ago
2004
ACM
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
156
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CODES
2009
IEEE
15 years 8 months ago
2009
IEEE
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a softwarelike ...
136
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ICCAD
2005
IEEE
16 years 1 months ago
2005
IEEE
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...
169
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GLVLSI
2003
IEEE
15 years 10 months ago
2003
IEEE
In this paper, we address the problem of the efficient exploration of the architectural design space for parameterized systems. Since the design space is multi-objective, our aim ...