897 search results - page 116 / 180 » System-Level Design for FPGAs |
140
Voted
VLSID
1999
IEEE
15 years 8 months ago
1999
IEEE
Formal approaches to HW and system design have not been generally adopted, because designers often view the modelling concepts in these approaches as unsuitable for their problems...
143
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DAC
2006
ACM
16 years 5 months ago
2006
ACM
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
171
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CODES
2003
IEEE
15 years 10 months ago
2003
IEEE
We present an approach to the automatic derivation of executable Process Network specifications from Weakly Dynamic Applications. We introduce the notions of Dynamic Single Assig...
141
Voted
ATS
2001
IEEE
15 years 8 months ago
2001
IEEE
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
145
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SP
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper presents a predictable and quantifiable approach to designing a covert communication system capable of effectively exploiting covert channels found in the various layer...