897 search results - page 121 / 180 » System-Level Design for FPGAs |
134
Voted
DAC
1997
ACM
15 years 8 months ago
1997
ACM
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...
120
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FPL
1997
Springer
15 years 8 months ago
1997
Springer
: The paper first proposes requirements for an ideal platform for codesign research. A new board developed at Imperial College, the Riley-2, is shown to meet these requirements. It...
116
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ARC
2007
Springer
15 years 8 months ago
2007
Springer
Abstract. This paper presents a methodology for the design of a reconfigurable computing system applied to a complex problem in molecular Biology: the protein folding problem. An e...
148
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FCCM
2009
IEEE
15 years 8 months ago
2009
IEEE
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
134
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FPL
2006
Springer
15 years 8 months ago
2006
Springer
In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This techniques can be used to identify registered cores for IP ...