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FPL
2008
Springer
104views Hardware» more  FPL 2008»
15 years 6 months ago
A technique for minimizing power during FPGA placement
This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...
Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Ya...
ASAP
2010
IEEE
193views Hardware» more  ASAP 2010»
15 years 6 months ago
Automatic generation of polynomial-based hardware architectures for function evaluation
Abstract--Polynomial approximation is a very general technique for the evaluation of a wide class of numerical functions of one variable. This article details an architecture gener...
Florent de Dinechin, Mioara Joldes, Bogdan Pasca
BCS
2008
15 years 6 months ago
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation
This paper describes our approaches to raise the level of abstraction at which hardware suitable for accelerating computationally-intensive applications can be specified. Field-Pr...
Qiang Liu, George A. Constantinides, Konstantinos ...
WSC
1998
15 years 6 months ago
Architecture for a Non-deterministic Simulation Machine
Causality constraints of random discrete simulation make parallel and distributed processing difficult. Methods of applying reconfigurable logic to implement and accelerate simula...
Marc Bumble, Lee D. Coraor
147
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FPL
2010
Springer
267views Hardware» more  FPL 2010»
15 years 2 months ago
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...
Gerald Hempel, Christian Hochberger, Andreas Koch