897 search results - page 124 / 180 » System-Level Design for FPGAs |
133
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NOCS
2007
IEEE
15 years 11 months ago
2007
IEEE
We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instance...
146
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ISQED
2006
IEEE
15 years 10 months ago
2006
IEEE
Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their ”expected delay” over input data space. This paradigm shift calls for ...
152
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FPL
2010
Springer
15 years 2 months ago
2010
Springer
A Multivariate Gaussian random number generator (MVGRNG) is an essential block for many hardware designs, including Monte Carlo simulations. These simulations are usually used in a...
117
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DATE
2009
IEEE
15 years 11 months ago
2009
IEEE
A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are ...
156
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CODES
2005
IEEE
15 years 10 months ago
2005
IEEE
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...