897 search results - page 125 / 180 » System-Level Design for FPGAs |
147
click to vote
CODES
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing arch...
131
click to vote
DATE
2003
IEEE
15 years 10 months ago
2003
IEEE
System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulat...
157
Voted
ASPDAC
2009
ACM
15 years 9 months ago
2009
ACM
— This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level M...
129
click to vote
DAC
2004
ACM
16 years 5 months ago
2004
ACM
Reconfigurable Systems-on-Chip (SoCs) on the market consist of full-fledged processors and large Field-Programmable Gate-Arrays (FPGAs). The latter can be used to implement the sy...
165
click to vote
DAC
2006
ACM
16 years 5 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...