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» System-Level Design for FPGAs
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LCTRTS
2009
Springer
15 years 11 months ago
Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring
The fine-grained parallelism inherent in FPGAs has encouraged their use in packet processing systems. Debugging and performance evaluation of such complex designs can be signifi...
Paul Edward McKechnie, Michaela Blott, Wim Vanderb...
FPGA
2004
ACM
180views FPGA» more  FPGA 2004»
15 years 10 months ago
A VHDL MPEG-7 shape descriptor extractor
Unlike its predecessors, MPEG-7 standardizes multimedia metadata description. By providing robust descriptors and an effective system for storing them, MPEG-7 is designed to provi...
Bret Woz, Andreas E. Savakis
FPL
2004
Springer
90views Hardware» more  FPL 2004»
15 years 10 months ago
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
Abstract. Layout tools for FPGAs can typically be run in two different modes: non-timing-driven and timing-driven. Non-timing-driven mode produces a solution quickly, without consi...
Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, ...
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
15 years 9 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
129
Voted
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
15 years 8 months ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...