897 search results - page 141 / 180 » System-Level Design for FPGAs |
247
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ICCAD
2003
IEEE
15 years 9 months ago
2003
IEEE
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
102
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FPGA
2003
ACM
15 years 9 months ago
2003
ACM
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we ...
141
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IPPS
1999
IEEE
15 years 8 months ago
1999
IEEE
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...
152
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GLVLSI
2007
IEEE
15 years 8 months ago
2007
IEEE
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
130
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ARC
2006
Springer
15 years 8 months ago
2006
Springer
Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much wo...