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FPL
2006
Springer
137views Hardware» more  FPL 2006»
15 years 8 months ago
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
FPL
2006
Springer
103views Hardware» more  FPL 2006»
15 years 8 months ago
An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures
Reconfigurable architectures are becoming increasingly popular with space related design engineers as they are inherently flexible to meet multiple requirements and offer signific...
Sajid Baloch, Tughrul Arslan, Adrian Stoica
FDTC
2008
Springer
87views Cryptology» more  FDTC 2008»
15 years 6 months ago
Silicon-level Solutions to Counteract Passive and Active Attacks
This article presents a family of cryptographic ASICs, called SecMat, designed in CMOS 130 nanometer technology by the authors with the help of STMicroelectronics. The purpose of ...
Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger,...
ERSA
2008
145views Hardware» more  ERSA 2008»
15 years 6 months ago
Multicore Devices: A New Generation of Reconfigurable Architectures
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...
Steven A. Guccione
ERSA
2006
99views Hardware» more  ERSA 2006»
15 years 5 months ago
Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdog...